发明名称 |
Semiconductor memory and layout/circuit information generating apparatus |
摘要 |
NMOS transistors which are provided adjacently to each other in the direction of the formation of bit lines between word lines are paired. The drains of the NMOS transistors are connected in common through a common node to form a memory cell. Between the common node and the bit line is provided a region where a contact is placed. Furthermore, regions where the contact is placed in the respective NMOS transistors are provided on a layout. By these combinations, data are stored.
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申请公布号 |
US5742540(A) |
申请公布日期 |
1998.04.21 |
申请号 |
US19970785826 |
申请日期 |
1997.01.15 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
WAKASUGI, HIROHIKO;MAENO, HIDESHI |
分类号 |
G06F17/50;G11C17/12;H01L21/8246;H01L27/112;(IPC1-7):G11C16/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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