| 摘要 |
A digital shift register contains a succession of master-slave flipflops (M/S) which are controlled by a clock signal (H), and also comprises, at least between two master-slave flipflops (M/S), a switching device (C) which enables selection of a serial loading mode or a parallel loading mode for the preceding flipflop. The switching device (C) contains a differential stage (Cs) which is used in the serial mode and which is composed of a pair of transistors (T1, T2), and a differential stage (Cp) which is used in the parallel mode and which consists of at least two differential pairs of transistors (T3, T4 and T3', T4') which are connected in parallel, only a part of the transistors of the output branch (T4') being connected to the input of the flipflop which succeeds the switching device, so that saturation of the input transistor (Te) of this flipflop (M/S) in the parallel loading mode is avoided.
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