| 摘要 |
A semiconductor memory device according to the present invention includes a pair of bit lines, a plurality of memory cells connected between the pair of bit lines, a sense amplifier, a pair of read bus lines connected to the sense amplifier, a first and second transistors provided between the pair of read bus line and the pair of bit lines, means for supplying a selection signal to gates of the first and second transistors, and a precharge circuit connected to the pair of read bus lines for precharging and equalizing the pair of read bus lines in response to an inversion of the selection signal, wherein a sum of parasitic capacitances between gates of a plurality of transistors constituting the precharge circuit and the read bus lines is equal to or larger than a sum of parasitic capacitances between gates of the first and second transistors and the read bus lines.
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