| 摘要 |
A detection circuit for detecting a simultaneous and identical access signal in a parallel processor. The detection circuit includes a cache memory, having multiple ports, for generating a SAME WAY HIT signal; a control signal generating circuit for generating and providing a control signal to the cache memory and for receiving the SAME WAY HIT signal from the cache memory; and adders for sending memory address signals, including a set address signal, to the cache memory through each of the multiple ports. Also included is a circuit for retrieving a set address signal from the memory address signals provided by the adders and for sending the set address signals to the control signal generating circuit, the set address being a part of a memory address signal; and an AND gate, provided the set address signals and the SAME WAY HIT signal to be sent to the control signal generating circuit, for comparing the set address signals to the cache memory and informing whether the set address signals are identical and simultaneously accessed or not.
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