| 摘要 |
<p>A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines (16a0-16a3), the drains of flash transistors in each column are coupled to common metal 1 lines (18a0-18a7) divided into even metal 1 lines and odd metal 1 lines and the sources of flash transistors are coupled to a common sourceline (20a). A set of first selection transistors (24a0-24a3) are coupled between even metal 1 lines and metal 2 lines (24a0-24a3) having a pitch twice that of the metal 1 lines and controlled by a first select signal (26a) to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistos (28a0-28a3) are coupled between the odd metal 1 lines and the metal 2 lines and controlled by a second select signal (26b) to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.</p> |
