| 摘要 |
A bit line discharge and sense circuit is provided for use with a static RAM that includes a row and column array of memory cells addressable via first and second bit lines and also a row select line. Each memory cell includes a transistor pair, wherein the first and second bit lines are coupled to an emitter of a first and second transistor comprising the transistor pair. The invention couples two current sources via the associated bit lines to the emitter of each transistor in the cell. A first current source is coupled when the cell is selected and provides a first current value having a bit line capacitance discharge current component and a first transistor read current component. A second current source is coupled to the same emitter when the cell is selected, and provides a lower current value. The first current source rapidly discharges capacitance associated with the associated bit line on the selected cell. The second, lower magnitude, current source is coupled to each bit line such that only the current difference between the first and second current sources flows through the selected cell. In this fashion the circuit rapidly discharges associated capacitance without subjecting the selected cell to excessive current flow. A voltage differential may be sensed directly via diode followers coupled to the emitter voltages to read the value of the selected memory cell.
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