发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE CELL WITH BURIED BIT LINE AND PIN STRUCTURED CAPACITOR
摘要 Cell manufacturing method is comprised of the step of forming a first insulating layer(122), a first conducting layer(124), a second insulating layer(126), a second conducting layer(128), and the second conducting layer(128) in succession on a substrate where a transistor, the buried bit line(120) surrounded by BPSG film(118) are formed, the BPSG film(118) to form a contact hole(130) for exposing a source region of the transistor, subsequently forming spacer made of the insulating layer for a part of a side of the first conducting layer(124) to be exposed to the inside of the contact hole(130), the step of forming the third conducting layer(132) in front of the result where the spacer is formed and forming a photoresist pattern(134) for forming a storage electrode on the third conducting layer, and the step of subsequently etching the third conducting layer, the second conducting layer, the second insulating layer, and the first conducting layer in succession to form the storage electrodes(124,128,132).
申请公布号 KR0132831(B1) 申请公布日期 1998.04.16
申请号 KR19940016453 申请日期 1994.07.08
申请人 SAMSUNG ELECTRONICS CO.,LTD 发明人 KIM, YOUNG-PIL;KIM, JONG-BOK;LEE, KWON-JAE
分类号 H01L27/08;H01L21/02;H01L21/8242;H01L27/06;H01L27/108;(IPC1-7):H01L27/08 主分类号 H01L27/08
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