| 摘要 |
A fabrication method of CMOS(complementary MOS) transistor is provided to decrease an isolation region of device and prevent a latch-up by forming the isolation region and floating well region using trench. The method comprises the steps of: forming a trench(2) in a first conductive well formation region of a semiconductor substrate(1); forming an insulating layer(3) on the resultant structure; exposing the semiconductor substrate(1) formed in the trench(2) by selective etching the insulating layer(3); growing an epitaxial layer(4) on the exposed semiconductor substrate; and forming a second conductive well(10) in the epitaxial layer(4). By forming the isolation region and floating well using the trench(2), it is possible to decrease the chip size and latch-up.
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