| 摘要 |
<p>A clock multiplexer including a plurality of clock selection circuits. Each clock selection circuit determines if a clock input is selected and provides the clock input to a clock output based on the determination. Each clock selection circuit futher includes deselect inputs, and a select input which is coupled to a deselect output, the deselect output providing a signal indicating if the select input is active. Each deselect input is connected to a respective one of the deselect outputs from the other clock selection circuits. In each clock selection circuit, the clock input is not provided to the clock output when one of the deselect inputs is active.</p> |
