| 摘要 |
PURPOSE:To improve an operation speed by simultaneously adding plural pairs of data. CONSTITUTION:The carry signal of each one bit full adder 13a-13d constituting a parallel adder is not transmitted to the next digit one bit full adder 13a-13d, and the carry signal is reflected on the carry bit of a flag register 16. Thus, one pair of data (two data) to be applied to a parallel adder 12 are recognized as the set of the plural data of a smaller size than the data size of one pair of data, and each data are simultaneously added without being interfered by a CPU. |
