| 摘要 |
PURPOSE:To generate a system clock whose phase is matched with a peak position in an analog clock signal always accurately. CONSTITUTION:The difference between a reference voltage value (u) corresponding to the rising edge of the system clock detected by the sampling circuit 4 of an analog ramp signal corresponding to the analog clock signal obtained by reproducing an optical disk, and an error voltage value (v) corresponding to a zero cross point in a differential signal differentiating the analog clock signal detected by the sampling circuit 7 by a differentiator 5 is detected by a difference detection circuit 14. Further, the difference between a correction voltage value (w) detected through the differentiators 8, 9 and the error voltage value (v) detected by the sampling circuit 7 is detected with the difference detection circuit 15 by the sampling circuit 13. Further, the detected result is operataed to 1/2 by an arithmetic circuit. Finally, after the differences as respective detected results detected by the difference detection circuits 14, 15 are detected by the difference detection circuit 17, the phase of the system clock is adjusted based on the detected result by a PLL circuit 18. |
