| 摘要 |
Disclosed is an image decoding apparatus having a frame memory structure. The apparatus comprises a data rearrangement part, a reciprocal difference pulse code modulator, the first, second and third frame memories(M1, M2, M3), a demultiplexer and an address generator. The data rearrangement part rearranges the reverse discrete data so that the data is transmitted in a parallel unit per pixel. The reciprocal difference pulse code modulator performs a reciprocal difference pulse code modulation to data from the data rearrangement part and from the movement compensated data. The first frame memory(M1) stores data from the reciprocal difference pulse code modulator. The second and third frame memories(M2, M3) store I and P picture data alternatively, and output the stored data when the write mode is not performed during the movement compensation. The demultiplexer selectively transmits data from the reciprocal difference pulse code modulator to the first, second and third frame memories(M1, M2, M3). Thereby, the image can be efficiently decoded only using the low frequency memories.
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