发明名称 CONFIGURATION SYSTEM FOR CLOCK SIGNAL SUPPLY SECTION
摘要 PROBLEM TO BE SOLVED: To suppress fluctuation in a frequency and a phase of a clock signal at system changeover attended with maintenance when clock signal supply sections consisting of 1st and 2nd systems and adopting the duplicate configuration enter a hold-over state through interruption of a clock path. SOLUTION: A branch output of a synchronization section 40 of a 1st system 10 is given to an input selector of a synchronization section 41 of a 2nd system 11 and a branch output of a synchronization section 41 of the 2nd system 11 is given to an input selector 30 of the 1st system 10 through a crossing loopback route, and as soon as a hold-over state is entered, an output clock signal of an active system is fed to a standby system so as to synchronize the standby system with the active system at all times.
申请公布号 JPH1098454(A) 申请公布日期 1998.04.14
申请号 JP19960253136 申请日期 1996.09.25
申请人 NEC CORP 发明人 YAZAKI MASAHIRO
分类号 H04L1/22;G06F1/04;H04L7/00 主分类号 H04L1/22
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