| 摘要 |
<p>PURPOSE:To obtain a polyphase clock at a speed proper to applications by eliminating a through-current of a clock driver of the polyphase clock generating circuit to reduce power consumption, power noise and ground noise and to change a delay between clocks optionally. CONSTITUTION:An input clock phi is used to control an output of a NAND gate 5m, a NOR gate 7m, a NAND gate 5n and a NOR gate 7n. The output of the 4 logic gates controls respectively a p-channel MOS transistor(TR) Pm and an n-channel MOS TR Nm of a clock driver 1m and a p-channel MOS transistor(TR) Pn and an n-channel MOS TR Nn of a clock driver 1n respectively and a through-current flowing between a power supply and a ground is eliminated by simultaneously turning off both the p/n-channel MOS TRs being components of the clock drivers 1m, 1n when the level of the output clocks phim, phin is changed.</p> |
