| 摘要 |
PROBLEM TO BE SOLVED: To provide a field effect transistor which can reduce a temporary parasitic bipolar current to a low level by a silicon-on-insulator technique. SOLUTION: A gap is provided between an insulator layer 20' and a source and/or drain region of a silicon-on-insulator(SOI) field effect transistor, and the gap is made smaller than the thickness of a depletion region 110 usually surrounding the source and/or drain region, preferably with a bias of 0V. The gain in a parasitic bipolar transistor formed, together with the field effect transistor, is temporarily decreased to increase an effective base/emitter junction capacitance only during an operational mode in which parasitic bipolar conduction dominates the normal operation of the field effect transistor. Such a temporary decrease in the gain combined with the temporary decrease of high frequency response is reduced to such an extent, that a parasitic bipolar current spike is larger than a previously obtained spike. And this technique has sufficient compatibility with other techniques for decreasing such a current spike. |
