| 摘要 |
PROBLEM TO BE SOLVED: To provide a mantissa normalizing circuit which is fast and small in scale. SOLUTION: To normalize an 8-bit mantissa, a cascade connection of a 4-bit left shifter 11, a 2-bit left shifter 12, and a 1-bit left shifter 13 is adopted. The 4-bit left shifter 11 makes a 4-bit left shift when C2=1, the 2-bit left shifter 12 makes a 2-bit left shift when C1=1, and the 1-bit left shifter 13 makes a 1-bit left shift when C0=1 respectively. Then C2=1 is set when the most significant 4 bits of the 8 input bits representing the mantissa to be normalized are all '0'-value bits, C1=1 is set when the most significant 2 bits of 8 bits supplied from the 4-bit left shifter 11 to the 2-bit left shifter 12 are both '0'-value bits, and C0=1 is set when the most significant bit of 8 bits supplied from the 2 bit left shifter 12 to the 1-bit left shifter 13 is a '0'-value bit. |
