| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock phase-locked circuit, where an output jitter/wander is reduced, without executing a circuit operation at high speed. SOLUTION: A shift register 4 delays a phase comparison result 301 by an output signal 141 and generates the phase of the phase comparison result. In plural phase difference detecting circuits 61-6N, the fluctuation of the phase is detected through the use of a sampling clock 161 and a fluctuation value judging circuit 7 which generates a fluctuation control signal 701. A digital phase difference adding/subtracting circuit 9 executes the addition/subtraction of the output digital phase comparison result 501 of a phase difference sampling circuit 5 and the fluctuation control signal 701 and generates digital control information 901, corresponding to a phase fluctuation which is smaller than the phase fluctuation which can be detected by the phase difference sampling circuit 5, so as to control the output of a voltage control oscillator 14. |
