| 摘要 |
PROBLEM TO BE SOLVED: To reproduce well the information after a PLL lock by surely executing PLL locking even in a short VFO area. SOLUTION: This Pll circuit is one, where a composite signal obtained by time sequentially arranging a repetition signal consisting of a fixed duty ratio pulse string and a random signal consisting of a pulse string where the change of a duty ratio is permitted, is supplied. The circuit is provided with a VCO (64), generating an output signal having a frequency corresponding to a control signal. PFC (60A) comparing the phase frequencies of the repetition signal and the output signal and generating a phase frequency differential signal, a PC (60B) comparing the phase of the random signal with that of the output signal and generating a phase differential signal, and LPF 62A and 62B extracting the prescribed band components of the phase frequency differential signal and the phase differential signal and generating the control signal. Thus, a PLL is formed by a phase frequency comparator, where a dynamic range is wide and an operation is executed in a single lock point at the time of reading VFO, so that a mis locking is eliminated and a sure pulling operation is attained in spite of the short VFO. |
