发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent the occurrence of phase deviation in phase error information outputted from a phase comparator even when a clock frequency becomes high. SOLUTION: Phase error information PDO outputted from a phase comparator is made a ternary signal of a first value (H), a second value (L), and a third value (Hi-Z), and when signals of the first value and the third value are outputted, the signals of the first value and the third value are continuously outputted. Thereby, even when a clock frequency is high, phase deviation caused by waveform distortion of outputted phase error information PDO is prevented.
申请公布号 JPH1097768(A) 申请公布日期 1998.04.14
申请号 JP19960267715 申请日期 1996.09.19
申请人 SONY CORP 发明人 KAWASHIMA TETSUJI
分类号 G11B20/14;G11B7/00;G11B7/005;H03L7/085 主分类号 G11B20/14
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