发明名称 SEMICONDUCTOR LOGICAL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To save power consumption and to execute a pull-up operation at a high speed by suppressing the rapid increase of a gate leak current, when a power voltage is larger than a gate-on voltage in a semiconductor logical circuit using a Schottky gate-type FET. SOLUTION: This circuit is composed of a push-pull circuit 100 and a DCFL (direct couple FET logic) logical circuit 200 and a transfer gate 6, the output b of the DCFL logical circuit 200 is connected to the gate of FET2 at a low- voltage power source side of the FETs constituting the push-pull circuit 100. The transfer gate 6 is connected to the input of the DCFL logical circuit 200 and the gate of FET1 at a high-voltage power source side of the FETs constituting the push-pull circuit 100 and its gate potential is adopted as a gate diode on voltage VF + a threshold value voltage VT. Thus, when the input IN becomes larger than VF, FET6 is turned off so that the gate leak current of FET3 is removed, and also the high level of the input IN is not clamped in VF. Therefore, the high level of the gate in FET1 becomes large, so that pull-up ability becomes large.
申请公布号 JPH1098367(A) 申请公布日期 1998.04.14
申请号 JP19960252138 申请日期 1996.09.25
申请人 NEC CORP 发明人 ATSUMO TAKAO
分类号 H03K17/04;H03K17/687;H03K19/0952 主分类号 H03K17/04
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