| 摘要 |
<p>Falling edges of a column address strobe (CAS) signal (109) are used to cause dynamic random access memories (DRAMs, 100) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches (102). A memory latch data (MLAD) signal (112) is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal.</p> |
