| 摘要 |
An apparatus for controlling a CMOS sensor array (2) containing a first CMOS sensor cell (cell 0), including a first logic circuit (30) for receiving a clock signal (clock) and generating a first address; a second logic circuit (36) coupled to the first logic circuit for receiving the first address and generating a reset signal to the first CMOS sensor cell based on the first address; a third logic circuit (34) coupled to the first logic circuit for receiving the first address and calculating a read delay based on the first address and an offset value; and a fourth logic circuit (32) coupled to the first logic circuit for generating a read address signal to the first CMOS sensor cell after the read delay.
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