| 摘要 |
<p>A plurality of FETs have their respective gates connected to each other through a first line and their respective drains connected to each other through a second line. A gate bias is applied to the gate of each FET through the first line and a drain bias is applied to the drain of each FET through the second line. A first matching circuit includes first capacitors connected to the signal path, inductors each connected between one end of each first capacitor and the ground potential, and second capacitors each connected between the other end of each first capacitor and the ground potential. The second matching circuit includes first capacitors each connected to the signal path, second capacitors each connected between one end of each first capacitor and the ground potential, and inductors each connected between the other end of each first capacitor and the ground potential. <IMAGE></p> |
