| 摘要 |
While a set-associative cache memory 14, 16 in a processing device 10 operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second, power-saving mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0<M<N. In the second mode, further power-saving is achieved by reducing the maximum number of data bits loaded from cache memory, or number of instructions fetched and processed, per cycle of the processing device. |
