| 摘要 |
The invention concerns a DRAM with an address space divided into blocks, in which the storage cells of the individual blocks are activated by an RAS signal (row address signal) delivered by a controller. Each individual block is activated by an independent activating signal derived from the RAS signal. The activating signal for the different blocks is transmitted to said blocks successively with partial time overlapping. The data flow obtained as a result of partially simultaneous activation of at least two different blocks is increased in comparison with activation of only one single block. |
