发明名称
摘要 PROBLEM TO BE SOLVED: To provide the device and method for test pattern compression which can compress a test pattern for a semiconductor integrated circuit. SOLUTION: This device consists of an attribute value checking means 11, a pattern value varying means 12, a repetitive pattern retrieval means 13, and a pattern looping means 14. The attribute value check means 11 checks the input/output attribute value and mask attribute value of the test pattern 101 and when the input/output attribute value is 'IO=0' and a master pattern is 'MASK=0', a test result is not compared; and a test pattern 102 is varied in pattern value by the pattern value varying means 12, the repetitive pattern retrieval means 13 retrieves whether or not the varied pattern 103 is a repetitive pattern, and the pattern looping means 14 loops the found repetitive pattern 104 and outputs it as a pattern-compressed test pattern 105.
申请公布号 JP2738357(B2) 申请公布日期 1998.04.08
申请号 JP19950221882 申请日期 1995.08.30
申请人 NIPPON DENKI KK 发明人 FUJITA YOKO
分类号 G01R31/3183;G06F5/00;G06F11/22 主分类号 G01R31/3183
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