| 摘要 |
An A/D converter includes a three-state comparator for detecting a higher state, a lower state and a equal state of a sampled analog signal with respect to a sequence of reference signals which are supplied from a counter or register after D/A conversion. After the equal state is detected, the D/A converter and the three-state comparator are stopped for power saving. The A/D converter further includes a frame memory and a control section which provide the counter or register with an initial code for each conversion cycle based on the last code of the previous conversion cycle constituting the previous digital output of the A/D converter. The A/D converter well follows the sequential change of the input level between the conversion cycles.
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