| 摘要 |
A method and circuitry for testing a memory in a computer system, to determine the sizes of individual memory banks, is disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes circuitry for enabling the selection of an individual memory bank of a memory, such as dynamic random access memory, which is arranged as multiple banks of arbitrary size. In operation, a memory bank is selected, and a first data word is written to the bottom memory address of the bank (which, for banks other than the first bank, is the top memory address of the previous bank). A second data word is written to a second memory location that is spaced apart from the bottom address by a trial value of the bank size. If the trial bank size is too small, the second data word will not overwrite the bottom address; if the trial bank size is accurate, however, the second data word will overwrite the bottom address, following which a register entry is made for the selected bank to indicate that its top memory address is the bottom address plus the determined bank size. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining memory address type.
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