LOW TEMPERATURE POLY-SILICON FILM STRUCTURE AND TRANSISTOR, AND MAKING METHOD THEREOF

摘要

A technique related to a polysilicon thin film is described that uses a Si-Ge alloy as a seed layer for controlling the cystalization of amorphous silicon. A Si-Ge alloy layer 10 and amorphous silicon layer 20 are sequentially deposited on a substrate 1, and then they are subject to an annealing process for a cystalization. Next, a gate pattern 50 is formed by patterning a first gate insulating layer 40, and a contact window is formed prior to forming of source and drain electrodes 70 and 70'. A thin film transistor includes the Si-Ge alloy layer 10 and silicon layer 20 sequentially formed on the substrate 1, the first gate insulating layer 40 formed on the silicon layer 20, a second gate insulating layer 60 formed on the first gate insulating layer 40 and provided with a contact window, and the source and drain electrodes 70 and 70' formed on the contact window. Thereby, it is possible to reduce cystalization time and improve the characteristic of a device.