REQUESTER READ CONTROLLER IN SYSTEM CONTROLLER IN SYSTEM CONTROL MODULE

摘要

Meditator(10) receives data calling signal of system bus from DMAC(2) or processor to be connected to system bus, then it meditates address bus for writing cycle, in case where it wins, outputs win signal to the first state controller(14). State Check Logic(1) decodes response to the transfer result of address or data through system bus to output it to the first and second state controller(14,15) and state register(16). After rack comparator(12) latches data from system bus to check if the latched data is of its own data, it outputs the resulting signal to the first and second state controller(14,15). The first and second state controller(14,15) transfers to be buffer ram of system controller the data of main memory transferred by state check logic(11) and rack comparator, and controls to execute reading cycle by processor.