| 摘要 |
<p>The encoder of coded image data includes a header detecting circuit(10) for detecting a first header, a second header and a third header from bit streams of an image coder and outputting clocks corresponding to the detected headers, a bit stream output control circuit(20) synchronized with the clocks, for in parallel outputting the bit streams at a predetermined bit, a recording controller(2) for controlling outputs of the bit stream output control circuit(20) to be selectively applied to FIFO buffers FIFO1 - FIFO4, and an interface detector for controlling the number of parallel output bits of the bit stream output control circuit(20) in response to the interface of slice which will be applied to the encoder. The coded image data amount to be processed by each of the encoders(101-104) is reduced as compared to the coded image data amount to be processed by one encoder so that the encoder having low operational frequency can desirably encode the coded image data.</p> |
