发明名称 Structure and method of manufacture for CMOS semiconductor device against latch-up effect
摘要 A semiconductor device comprises a semiconductor substrate of a first conductivity type, a well which is a second conductivity type, a buried layer, which is of the first conductivity type, and an insulating isolation layer formed extending to an upper surface of a side region of the well. The buried layer has a first portion of a higher dopant concentration than the semiconductor substrate and formed in a deep region of the semiconductor substrate directly below the well, and a second portion formed in a region of the substrate which is positioned higher than the region in which the first portion is formed. The first and second portions of the buried layer are formed integrally in a region of the semiconductor substrate which is directly below the insulating isolation layer, surround the well within the semiconductor substrate, and have a high concentration of a dopant that is of the first conductivity type at a position which is directly below the insulating isolation layer. A transistor of the first conductivity type is formed at the well and a transistor of the second conductivity type is formed in the semiconductor substrate above the second portion of the buried layer.
申请公布号 EP0794575(A3) 申请公布日期 1998.04.01
申请号 EP19970108675 申请日期 1988.10.06
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 ODANAKA, SHINJI
分类号 H01L21/74;H01L21/8238;H01L27/092 主分类号 H01L21/74
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