发明名称 Semiconductor memory device with a plurality of memory cells connected to bit lines and method of adjusting the same
摘要 When the upper limit value of a leakage current allowed by a read.detection/write circuit connected to a plurality of bit lines to read and write data from and in memory cells is represented by IL, Vs satisfies <IMAGE> (ln is the natural logarithm) where Vgh is the potential of a non-selected word line, Vta is the average threshold voltage of the memory cells, e is the standard deviation, s is the subthreshold coefficient, Vd is the potential of the bit lines, and Vs is the potential of a source line.
申请公布号 US5734612(A) 申请公布日期 1998.03.31
申请号 US19960674820 申请日期 1996.07.03
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YOSHIKAWA, KUNIYOSHI
分类号 G11C17/00;G11C16/06;G11C16/26;G11C16/34;G11C17/08;G11C29/02;G11C29/50;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/00 主分类号 G11C17/00
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