| 摘要 |
A DRAM includes a word driver unit, a subword driver block, a memory array block, a control circuit, a decode circuit, an equalize block, a sense amplifier block, and an I/O switch unit. A plurality of main word line run through the memory array block. A plurality subword lines are connected to each main word line. A division word line structure and an address non-multiplex method are applied in the DRAM. Therefore, the sense amplifier block can be used as a cache memory. The number of ways of the cache can be increased to improve the hit rate without increase in the chip area.
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