| 摘要 |
A compact input/output processing IC, which reduces the CPU load, to which microcomputer 100, input/output processing IC 200, and various inputs and outputs are connected. Parallel signals are connected to a high-speed input/output buffer and serial signals are connected from communications control circuit 207 via serial communications circuit 206 to SIO 104. To achieve the proper control, data requiring high speed is handled by parallel communications. Serial communications is handled by shift registers, first bit of each being connected to the last bit of the other, to form a loop, with instruction and input/output data from the CPU exchanged simultaneously, thereby achieving efficient processing. This achieves better organization of the communications for input/output processing, enabling both better control and a compact hardware design.
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