发明名称 CHANNEL ENCODER FOR DIGITAL COMMUNICATION
摘要 PURPOSE: A channel encoder for the digital communication is provided to carry out a convolutional-encoding and an interleaving operation at once by using two LAMs for buffering a frame input data having the low memory usage alternately. CONSTITUTION: The device carries out a convolutional-encoding and interleaving operation of a frame input data at once by using two encoder RAMs(417). A microcontroller controls to store a frame input data input to a frame input data register(411) into the first encoder RAM(416) while parallel-inputs into a parallel CRC generator(412) generated by the number of a given CRC input bit and a production polynomial. A device carries out an XOR logic-operation of the input parallel CRC input value and the previous CRC state value to parallel calculate a desired CRC output value. A device stores the CRC output value with the frame data stored in the first encoder RAM and reads the stored CRC output value to carry out the convolutional encoding and the interleaving. The convolutional encoding and interleaving for the frame input data, and storing the next frame input data into the second encoder RAM are carried out at once.
申请公布号 KR20010009726(A) 申请公布日期 2001.02.05
申请号 KR19990028261 申请日期 1999.07.13
申请人 KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 CHO, HAN JIN;KIM, GYEONG SU;LIM, IN GI
分类号 H03M13/00;(IPC1-7):H03M13/00 主分类号 H03M13/00
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