| 摘要 |
A decoding unit decodes data reproduced from a recording medium and obtained via first phase locked loop (PLL) and second PLL which are mutually independent and oscillate at frequencies which are approximately the same, where the recording medium is recorded with pulse width modulation (PWM) data which are obtained by converting data encoded by a predetermined modulation code that generates a pattern having a D.C. component. The decoding unit includes a first storage for successively storing a positive polarity data portion of the PWM data obtained via the first PLL and a negative polarity data portion of the PWM data obtained via the second PLL, a first delay for delaying the positive polarity data portion, a second delay for delaying the negative polarity data portion, a second storage for successively storing a delayed positive polarity data portion obtained via the first delay and a delayed negative polarity data portion obtained via the second delay, a controller for controlling write and read timings of the first storage and input and output timings of the first delay in synchronism with a first clock obtained via the first PLL, and for controlling a write timing of the second storage and an input timing of the second delay in synchronism with a second clock obtained via the second PLL, where the controller controls a read timing of the second storage and an output timing of the second delay in synchronism with the first clock, and a decoder which decodes the data successively read from the first and second storages.
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