Multiprocessor with split transaction bus architecture for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag

摘要

A method of arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase, and arranged for access by a prescribed resource stage, to facilitate "RETRY", this method including; providing a Cache Tag and Address Compare, arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; and comparing subsequent address bus cycles to the contents of the Cache Tag so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access.