| 摘要 |
A disk accelerator being a new design for caching disk controller includes caching disk control unit which contains an address mapper therein, which is a pure hardware logic. The address mapper maps the disk location parameters being accessed into an effective address. A cache memory and a tag memory contained in the disk accelerator are similar to that of normal memory caches, except that the effective address and sector(s) are used as memory address and memory word(s) respectively. The disk accelerator can provide real time response on cache hit or miss, and can also eliminate the overhead for manipulating buffer. The disk accelerator can be implemented by a single VLSI chip with a sizable memory constitutes of SIMMs or DRAM chips or other memory chips.
|
