发明名称 CONTROL SYSTEM FOR RATE CONVERSION BUFFER FOR ATM CELL
摘要 PROBLEM TO BE SOLVED: To reduce a capacity of a buffer memory, to decrease a cell delay and to conduct quickly a restoration processing in the case that synchronization is disturbed by reducing a residence of cell in a buffer memory in a rate conversion buffer control system of a subscriber interface section of an ATM asynchronous transfer mode exchange. SOLUTION: A rate conversion buffer of a subscriber interface section of an ATM exchange is provided with a timing discrimination means 11 discriminating a phase relation of read request signals from a common section in duplicate and a timing decision means 12 to decide a read timing according to a discrimination result signal from the timing discrimination means 11. Then an ATM cell is read out of buffer memories of an active system and a standby system depending on the timing decided by the timing decision means 12.
申请公布号 JPH1079739(A) 申请公布日期 1998.03.24
申请号 JP19960232933 申请日期 1996.09.03
申请人 FUJITSU LTD 发明人 YOSHIZUMI NOBUTAKA
分类号 H04Q3/00;H04L12/28;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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