| 摘要 |
A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the Vss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's Vss clamp diode (stored charge in the Vss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's Vss clamp out of forward conduction. Driver sizing can control the problem. Lower current will turn the clamp on for a shorter amount of time, and change the position of the ring. Improved modeling or simulation can allow selection of correct driver sizes and other circuit elements.
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