发明名称 |
Multi-function microprocessor wait state mechanism using external control line |
摘要 |
A wait state mechanism for lengthening a microprocessor's bus cycle to allow data transfers between slower off-chip devices. A microprocessor is responsive to a bus control signal generated by external programmable logic which instructs the microprocessor to insert wait states of varying number depending on the component involved in a bus transaction. The microprocessor receives only a single input from the programmable logic and varies its bus cycle length accordingly.
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申请公布号 |
US5732250(A) |
申请公布日期 |
1998.03.24 |
申请号 |
US19970786393 |
申请日期 |
1997.01.20 |
申请人 |
INTEL CORPORATION |
发明人 |
BATES, LARRY;GARBUS, ELLIOT |
分类号 |
G06F13/42;(IPC1-7):G06F1/12 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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