发明名称 |
Chip sizing for hierarchical designs |
摘要 |
A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit in such a manner that the fractional change in the percentage occupancy is substantially constant among all macro cells at all hierarchy levels.
|
申请公布号 |
US5731985(A) |
申请公布日期 |
1998.03.24 |
申请号 |
US19960631113 |
申请日期 |
1996.04.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GUPTA, RAJESH;SAYAH, JOHN YOUSSEF |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|