| 摘要 |
A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock signal. The circuit receives an input clock signal and an input clock enable signal. The circuit generates an output clock signal which is an enabled/disabled version of the input clock signal, controlled by the input clock enable signal. The circuit thus provides the operational advantages of enabling or disabling, with a single control signal, groups of logic circuits triggered by a common clock signal.
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