发明名称 |
Process for global planarization of memory and globally planarized memory |
摘要 |
A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate. |
申请公布号 |
US5731234(A) |
申请公布日期 |
1998.03.24 |
申请号 |
US19960669965 |
申请日期 |
1996.06.25 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
CHEN, ANCHOR |
分类号 |
H01L21/8239;H01L21/8242;(IPC1-7):H01L21/70 |
主分类号 |
H01L21/8239 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|