| 摘要 |
PROBLEM TO BE SOLVED: To generate a highly accurate synchronizing clock signal in a comparatively wide frequency range by latching respective outputs from a specific variably delay means group by a synchronizing trigger signal, selecting plural signals from the outputs of the variable delay means group in accordance with the latched output and switching the selected signals in accordance with a latch output. SOLUTION: A duty reproducing part 11 reproduces the duty of a clock signal to 50% and a latch part 13 latches respective outputs from the variable delay means group 12 of which delay quantity is To.M/N (To is a period and M and N are integers) by a synchronizing trigger signal NHD. A selection part 14 selects 1st and 2nd signals from the outputs of the group 12 in accordance with the latched outputs and a delay means 15 delays the 1st selected output. A delay means 16 delays the trigger signal NHD and a latch 17 latches the output of the means 15 by the output edge of the means 16. A switching means 18 switches the output of the means 15 and the 2nd output of the selection part 14 in accordance with the output of the latch 17 and outputs a synchronizing clock signal. |
