Semiconductor memory device including main/sub-bit line arrangement

摘要

A semiconductor memory device including a plurality of sub-bit lines, a sense amplifier provided in common to the plurality of sub-bit lines which receives a data signal from a first one of the plurality of sub-bit lines, a main-bit line operatively coupled to the sense amplifier to receive an output of the sense amplifier, and a data latch circuit provided to latch data appearing on the main-bit line. The device further comprises a circuit for transferring a data signal of a second one of the plurality of sub-bit lines to the sense amplifier when the data latch circuit is being accessed to read out data latched in the data latch circuit.