The invention concerns a DRAM cellular arrangement comprising a vertical MOS transistor in every memory cell. The first source/drain area (4) of said transistor is connected to a storage node of a memory condenser (4, 15, 16), the channel area (3) of which is surrounded annularly by a gate electrode (13). The second source/drain area of the channel area is connected to a buried bit line (2). The DRAM cellular arrangement is produced by using only two masks assisted by a spacer with a memory cell surface of 2F<2>, whereby F represents the minimum structural size that the relevant technology can produce.
