Reduction of clock skew

摘要

The clock input to an IC is delayed 64 so that an input data signal can be latched without contravening set-up and hold times. The delay time is controlled 65 in response to a phase detection circuit 70 monitoring the relation between the input data and the output of the latch 62 during a calibration mode (figure 12) in which the transmitting IC sends an alternating data sequence that has its edges aligned with the rising clock edges. The delay setting is fixed and transmitted data is then sent with its transitions aligned to the falling clock edges. Circuits are disclosed that adjust the clock delay continually during normal data transfer so that no initial calibration mode is required (figure 13). Circuits are disclosed that equalise time delays of data channels (figure 46).