| 摘要 |
<p>PCT No. PCT/GB93/00792 Sec. 371 Date Oct. 14, 1994 Sec. 102(e) Date Oct. 14, 1994 PCT Filed Apr. 15, 1993 PCT Pub. No. WO93/21659 PCT Pub. Date Oct. 28, 1993An integrated circuit arrangement comprising a pair of double-gated insulated-gate transistor devices connectible in series, the first transistor of the pair being biased by one of the gates of the device so as to be operable as a depletion-mode device whilst the second transistor of the pair is biased by one of its two gates so as to be operable as an enhancement-mode device. The separately-biasable gate electrode permits the threshold voltage of the transistors to be adjusted independently so that the device may operate as either a depletion-mode transistor or as an enhancement mode transistor.</p> |
